With the miniaturization and multifunctionalization of electronic devices, semiconductor devices have also been highly integrated and multifunctionalized. As a result of such demands, a Multi-chip Package (MCP) semiconductor device in which a plurality of chips are integrated has been introduced. MCP semiconductor devices may be classified into single-layer MCP semiconductor devices and multi-layer MCP semiconductor devices. The single-layer MCP semiconductor device can be packaged by arranging a plurality of chips in a regular line, and the multi-layer MCP semiconductor device, which is generally known as a stacked semiconductor device, can be packaged by stacking a plurality of chips.
A stack-type semiconductor device can have a plurality of stacked chips and thus have a three-dimensional structure. A conventional stacked semiconductor device can connect input/output terminals on a plurality of chips to each other or connect the input/output terminals of each of the chips to its external connection terminal through wire bonding, and thus inputs/outputs various signals. However, the use of wire bonding can deteriorate the performance of the semiconductor device due to an increase in inductance, and can increase the size of the semiconductor device.
Wafer-level processed Stack Package (WSP) technology has also been developed. According to the WSP technology, a via hole vertically penetrating a plurality of stacked chips can be formed using a laser at wafer level and is filled with a through-silicon via (TSV) to directly connect the circuits of the respective stacked chips. A stacked semiconductor device employing the WSP technology can directly connect the respective stacked chips and thus may avoid utilizing a discrete wire. In addition, a vertical interval between the chips may be reduced, and thus it may be possible to decrease the thickness of the stacked semiconductor device. Furthermore, the mounting area of the semiconductor device may be reduced.
In a stacked semiconductor device employing the WSP technology, transfer paths for transferring signals between a plurality of stacked chips may be roughly classified into two types. One type is a parallel path through which the same signal is simultaneously transferred to multiple chips, and the other type is a serial path in which a chip receiving a signal performs a specific operation in response to the applied signal and then transfers the applied signal or a signal generated as the result of the operation to another chip in sequence. This is sometimes referred to as a “daisy-chained” configuration.
FIGS. 1A and 1B are conceptual diagrams of a parallel path and a serial path of a stacked semiconductor device using the WSP technology, respectively.
FIGS. 1A and 1B illustrate an example of a four-stage stacked semiconductor device in which four chips C1 to C4 are stacked. In FIG. 1A, a parallel line PL is connected to all of the chips C1 to C4 and simultaneously transfers an input common signal SC to the four chips C1 to C4. Internal circuits 11 to 14 respectively included in the four chips C1 to C4 perform designated operations in response to the common signal SC and output common output signals SCO1 to SCO4, respectively. The common output signals SCO1 to SCO4 respectively output from the four chips C1 to C4 may be identical to or different from each other. In addition, the four chips C1 to C4 may not output the common output signals SCO1 to SCO4.
In FIG. 1B, serial lines SL1 to SL4 are connected in a daisy-chained configuration. The serial line SL2 is connected between the chips C1 and C2, and the serial line SL3 is connected between the chips C2 and C3. Therefore, the serial lines SL1 to SL4 may not directly transfer the same signal to all of the stacked chips C1 to C4, but rather components are interspersed. Internal circuits 21 to 24 receive an input signal SI applied from outside and output signals SO1 to SO3 applied from previous chips through the serial lines SL1 to SL4, perform designated operations and output the output signals SO1 to SO4, respectively.
In general, a stacked semiconductor device utilizes all of the parallel line PL and the serial lines SL1 to SL4. For example, signals transferred through the parallel line PL can be a command signal, an address signal, a data signal, a control signal, an input/output signal, etc., and signals transferred through the serial lines SL1 to SL4 can be a chip Identification (ID) signal, a test signal, etc. Besides the above mentioned signals, a drive voltage such as a supply voltage or a ground voltage, for driving the respective chips C1 to C4 may be transferred through the parallel line PL or the serial lines SL1 to SL4.
However, the signals are not set to be necessarily transferred through the parallel line PL or the serial lines SL1 to SL4. Rather, the respective signals are set to be transferred through the parallel line PL or the serial lines SL1 to SL4 according to the semiconductor device and functions of the respective chips C1 to C4.
In FIG. 1A, the parallel line PL is connected to all of the stacked chips C1 to C4 and thus can be disposed at the same positions in the respective chips C1 to C4. In other words, the positions of the parallel line PL in the respective chips C1 to C4 can be identical. On the other hand, in FIG. 1B, the serial lines SL1 to SL4 can be disposed at different positions in the respective chips C1 to C4. Therefore, the respective chips C1 to C4 can be designed such that the serial lines SL1 to SL4 are disposed at the same positions as in adjacent chips. In addition, via holes are formed at different positions in the respective chips C1 to C4, and thus the respective chips C1 to C4 can utilize separate processes. Therefore, the patterns of the chips C1 to C4 can be designed in consideration of the positions of the serial lines SL1 to SL4 in adjacent chips.
FIGS. 2A and 2B illustrate two chips having different patterns and a stacked semiconductor device in which a parallel path and a serial path can be formed by stacking the chips, respectively.
As mentioned above, when the positions of serial lines in respective chips differ from each other in a stacked semiconductor device having a plurality of chips, the plurality of chips stacked in the stacked semiconductor device can be configured to form a parallel path and a serial path regardless of the number of the stacked chips even if the chips have only two patterns.
In FIG. 2A, a first chip PA and a second chip PB have different via hole patterns, and the respective via holes are filled with through-silicon vias TSV. On one surface of the respective chips PA and PB, bumps MB are prepared for electrically connecting the chips PA and PB with the through-silicon vias TSV of adjacent chips and forming a space between the chips PA and PB. In addition, between the through-silicon vias TSV and the bumps MB on the chips PA and PB, internal circuits (not shown) are prepared for performing designated operations.
FIG. 2B illustrates a stacked structure of the first and second chips PA and PB. On the parallel lines PL of the chips PA and PB shown in FIGS. 2A and 2B, the through-silicon vias TSV and the bumps MB are disposed at the same position. On the other hand, on the serial line SL of the chips PA and PB, the through-silicon vias TSV and the bumps MB are disposed at different positions because the internal circuits are provided between the through-silicon vias TSV and the bumps MB.
As illustrated in FIGS. 2A and 2B, in a stacked semiconductor device including chips having two patterns, a parallel path and a serial path can be formed according to the positions of the through-silicon vias TSV and the bumps MB constituting the parallel lines PL and the serial lines SL regardless of the number of the stacked chips having the two patterns. Therefore, in order to design an internal circuit of a chip, one of the two patterns is selected according to a position where the chip is disposed, and only the positions of the through-silicon vias TSV and the bumps MB designated to the selected pattern may be considered. In other words, it may not be necessary to consider the pattern of an adjacent chip. In addition, since there are only two patterns, processes for forming a parallel path and a serial path may also be limited to two types.